System, structure, and method of manufacturing a semiconductor substrate stack

ABSTRACT

A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

This application claims the benefit of U.S. Provisional Application Ser. No. 61/127,627, filed on May 14, 2008, entitled “System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack,” which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to a system, a structure, and a method of forming a semiconductor substrate stack, and particularly to forming a semiconductor substrate stack using a through substrate via (TSV).

BACKGROUND

As the cost of shrinking CMOS devices continues to increase, alternative approaches, such as extending the integration of circuits into the third dimension or semiconductor substrate stacking are being explored. Thinned substrates connected by TSVs can reduce the height and width of a packaged chip stack relative to current wire bonding technologies. Performance may also be enhanced because of TSV implementation in stacked chip designs.

Several methods of producing stacked substrates and TSVs have been implemented; including stacking wafers back-to-back, back-to-front, front-to-front, and chip stacking, for example. One known method of producing front-to-front stacks may include forming the TSV structures at the first interconnect level of the front end of line (FEOL) process. The method may include patterning and etching connecting vias into the backside of the wafer after thinning. One disadvantage of this method may be the difficulty of aligning a connecting via on the backside of a thinned wafer with a prior formed TSV structure. Misalignment may result in no connection to the TSV structure, or a limited connection to the TSV structure. Further, the diameter of a backside via structure employed to connect with a TSV may be smaller than the TSV. This may cause additional problems in clearing the sacrificial material from the prior formed TSV. A TSV/backside via structure may be more resistive if the sacrificial material is not sufficiently removed. Moreover, another disadvantage of the prior formed TSV is the cost of the photo procedure to pattern the backside of the wafer.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved by a system, structure and method of forming a semiconductor substrate stack using a through substrate via (TSV) structure.

In accordance with an illustrative embodiment, an integrated circuit device is provided. The integrated circuit device includes a substrate having an active region formed therein, a via extending through the substrate, having a first termination substantially aligned with a bottom surface of the substrate and a second termination substantially aligned with a top surface of the substrate. A first conductive contact is electrically connected to the second termination of the via and electrically connected to a conductive interconnect layer. A second conductive contact is electrically connected to the conductive interconnect layer and the active region.

In accordance with another illustrative embodiment of the present invention, a semiconductor substrate is provided which includes a front-face, a backside, a bulk layer with a plurality of sub-bulk layers, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

In accordance with another illustrative embodiment of the present invention, a method manufacturing a semiconductor substrate structure is presented. The method includes etching a TSV structure into a front-face of a substrate before a FEOL contact process. The TSV structure is coated with a liner, filled with a sacrificial material, and provided with an etch stop layer (ESL). The method includes forming at least a first contact between the TSV structure and an interconnect layer and forming at least a second contact between an active region and an interconnect layer. A substrate backside is thinned and a bulk material is recessed to expose a bottom liner of the TSV structure. A hard mask passivation layer is disposed. The substrate backside is planarized exposing the sacrificial material. The sacrificial material is etched, and the ESL is removed. The TSV structure is then filled with a conducting material. A dielectric topside layer is deposited and a backside bonding pad is disposed. The backside bonding pad is electrically coupled to the TSV structure.

An advantage of an illustrative embodiment of the present invention is that the cost of the photolithography step to open vias on the backside of the substrate to contact the TSV structures is eliminated.

A further advantage of an illustrative embodiment of the present invention is the sacrificial material may be removed thoroughly, without misalignment and other associated disadvantages to the backside via pattern and etch process.

The foregoing has outlined rather broadly the features and technical advantages of an illustrative embodiment in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of an illustrative embodiment will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the illustrative embodiments as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the illustrative embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross sectional depiction of a semiconductor substrate stacking system, in accordance with an illustrative embodiment;

FIGS. 2A-2I are cross sectional depictions of a semiconductor substrate stacking system during selected process steps of an illustrative embodiment; and

FIG. 3 is a flow chart of a method of forming a semiconductor substrate stacking system.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that an illustrative embodiment provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to illustrative embodiments in a specific context, namely a front-to-front stacked semiconductor substrate system. The invention may also be applied, however, to other semiconductor substrate systems, such as single substrates, back-to-back bonded substrates, chip stacks, multiple substrate stacks, and the like. Embodiments may also have application in other through substrate via processes.

With reference now to FIG. 1, a system for stacking semiconductor substrates is shown. The term “substrate” herein, generally refers to a semiconductor substrate including a bulk layer 110 on which various layers and structures are formed. Silicon may be used or compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. Example layers may include such layers as dielectric layers, doped layers and polysilicon layers. Example structures may include transistors, resistors, and/or capacitors, which may or may not be interconnected through an interconnect layer to additional active circuits.

System 100 shows substrate-A 102 inverted and bonded to substrate-B 104 at bonding joint 106. In an embodiment shown, front-face-A 103 of substrate-A 102 is bonded to front-face-B 105 of substrate-B 104 at bonding joint 106. Substrate-A 102 comprises interconnect layer 108, contact layer 109, bulk layer 110, and backside connection layer 112. Circuit-A 114 is also shown. Circuit-A 114 may extend from the upper layers of bulk layer 110 through contact layer 109 to interconnect layer 108.

Through substrate via (TSV) structures 116 are shown in substrate-A 102 and not in substrate-B 104. However, substrate-B 104 may have TSV structures in another embodiment. In yet another embodiment, multiple substrates may be stacked one on the other in front-to-front, front-to-back, and back-to-back configurations. TSV structures 116 may have lining 117 comprising a dielectric such as an oxide, nitride, or the like. TSV structures 116 are filled with a conductive material such as Al, Cu, other metals, alloys, doped polysilicon, combinations, and the like. Preferably, TSV structures 116 are filled with metal.

Semiconductor circuits, such as circuit-A 114, are manufactured by forming active regions in a bulk layer, such as bulk layer 110, depositing various insulating, conductive, and semiconductive layers over the substrate, and patterning them in sequential steps. The interconnect layer typically provides connections to underlying active regions and connections within and over the substrate. The interconnect layer includes one or more layers of metal interconnect having the conductive lines disposed within an insulating material. A contact layer, such as contact layer 109 is comprised of conductors disposed in dielectrics, which connect components in bulk layer 110 of substrate-A 114 to interconnect layer 108. The conductors in the contact layer may be any conducting material such as doped polysilicon, Al, Cu, W, alloys, combinations, and the like. Preferably, the contact material is W. Dielectrics in the contact layer may be oxides, nitrides, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass or fluorinated silicon oxide glass (FSG) or any electrically isolating materials.

TSV structures 116 are etched prior to contact layer 109 of circuit-A 114. Contacts 118 provide electrical coupling between the TSV structures 116 and interconnect layer 108. Backside connection layer 112 provides electrical interconnection between substrate-A 102 and outside systems, which may include other stacked substrates. Through bonding joint 106 backside connection layer 112 may also provide electrical interconnection between substrate-B 104 and outside systems. Backside connection layer 112 is comprised of a backside dielectric 120 and backside metal 122. Backside dielectric 120 may be, for example, a layer of SiN and a layer of an undoped silicon oxide glass (USG), or the like.

FIGS. 2A-2I are cross sectional depictions of a semiconductor substrate stacking system during selected process steps of an illustrative embodiment.

FIG. 2A shows substrate-A 102 with front-face 103 oriented up, as may be typical during circuit processing, and with TSV structures 116 oriented down into bulk layer 110 (note that substrate-A is shown oriented “flipped” relative to FIG. 1). Circuit-A 114 is shown prior to contact etch.

Bulk layer 110 may be patterned, for example, by depositing a photoresist 222 over the top surface of bulk layer 110. Using a reticle, having transparent regions and opaque regions, photoresist 222 or a hard mask may be patterned using techniques well known in the art. In an embodiment implementing a hard mask, the resulting TSV structure may then terminate substantially the thickness of the hard mask above the substrate, rather than substantially at the substrate. The TSV structures may be etched using a reactive-ion plasma process for example. A Bosch process, which is capable of achieving high aspect ratio structure, may be implemented in an embodiment. In an alternate embodiment a wet etch may be implemented. The TSV structures may range in depth from tens to hundreds of microns.

TSV structures 116, thus etched, are coated with a dielectric layer, such as SiO₂ or SiN to form liner 117, as shown in FIG. 2B. Liner 117 may be comprised of oxides, nitrides, combinations, or other dielectrics. Preferably, the liner is SiO₂, formed in a wet oxidation process.

Liner 117 may act as a passivation layer between bulk layer 110 and the subsequent metal conductor filled into TSV structures 116. An advantage of an illustrative embodiment is that high quality dielectrics may be more readily used in this step of the substrate processing.

TSV structures 116 are then filled with sacrificial material 226. The sacrificial material may be a nitride, an oxide, a doped or undoped polysilicon, or the like. One consideration of the choice of sacrificial material may be a high etch selectivity between liner 117 and subsequently deposited etch stop layer (ESL) 224. In the illustrative embodiment shown, undoped polysilicon is used to fill into the TSV structure. After deposition, a planarization process may be performed to remove any undoped polysilicon formed outside of the TSV structure.

TSV structures 116 are then capped with a dielectric layer, which acts as an ESL 224 during the subsequent etch of sacrificial material 226 (described in FIG. 2H). ESL 224 may comprise oxide, nitride, other dielectrics, combinations, or the like. ESL 224 is preferably SiO₂. One consideration of the choice of ESL material may be a high etch selectivity between the ESL material and liner 117 plus the subsequently deposited hard mask (described further in FIG. 2G).

Turning to FIG. 2C, an insulating material layer 228 is then disposed on bulk layer 110. Insulating material layer 228 may be, for example, SiON, SiN, PSG, combinations, or the like. Insulating material layer 228 may be patterned and openings for contacts 230 may be etched. Contacts 230 may be comprised of metal, such as W, Al, Cu, combinations, or the like, filling the contact openings. Alternatively, contacts 230 may be formed of doped polysilicon or other sufficiently conductive material. Contacts 230 are formed in insulating material layer 228. Contact layer 109 comprises insulating material layer 228 and contacts 230. Note that some contacts 230 found in contact layer 109 may contact the TSV structures 116 and other contacts 230 found in contact layer 109 may contact circuit-A 114.

Turning now to FIG. 2D, interconnect layer 108 is shown. A single substrate may contain many active regions and/or functioning circuits. For example, bulk layer 110 may include one or more semiconductor elements, e.g. transistors, diodes, etc. (not shown) and circuit-A 114. Bulk layer 110 may also include other active components or circuits formed therein. At times, it is necessary to connect one circuit or device with another circuit or device that is not immediately adjacent to it. An interconnect layer, such as interconnect layer 108 may be used for this purpose.

Interconnect layer 108 may be comprised of a series of inter-metal dielectric (IMD) and conductive lines interconnected by vias (not shown). Interconnect layer 108 is further comprised of metal and inter-metal dielectrics, formed by disposing alternate layers of metal and inter-metal dielectrics. Conductive lines may comprise Cu, Al, W, other conductive material, or combinations thereof, as examples. One or more barrier layers and seed layers may be deposited prior to the deposition of the Cu, Al, W, other conductors, or combinations thereof, for example (not shown). The conductive lines may be disposed employing a damascene process, a dual damascene process, an etched conductive layer process, or the like. Different layers of the multilayered interconnect layer 108 may be comprised of different materials. Top metal 240 is formed for bonding substrate-A 102 to another substrate, or system. For example, top metal 240 may employed for use as a bonding joint, such as bonding joint 106, in FIG. 1. Top metal 240 may comprise Cu, Al, other metals, combinations, other conductors, and the like.

The insulating layers or inter-metal dielectrics described herein may comprise traditional insulating materials used for interconnect layers such as SiO₂, or alternatively may comprise low-κ materials. The low-κ material may comprise diamond-like carbon, such as Black Diamond™ by Applied Materials, Inc., phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass or fluorinated silicon oxide glass (FSG), SiO_(x)C_(y), Spin-On-Glass, Spin-On-Polymers, SILK™ by Dow Chemical, FLARE™ by Honeywell, LKD (low-κ dielectric) from JSR Micro, Inc., hydrogenated oxidized silicon carbon material (SiCOH), amorphous hydrogenated silicon (a-Si:H), SiO_(x)N_(y), SiC, SiCO, SiCH, compounds thereof, composites thereof, and/or combinations thereof, as examples. In other applications, the insulating layers 218 may comprise a high dielectric constant material, having a dielectric constant of greater than about 4.0, for example. The insulating layers 218 may alternatively comprise a combination of one or more low-κ materials, high-κ material, SiO₂, SiN, or combinations, for example.

There may be one, or a plurality of metallization layers included in interconnect layer 108, for example (not shown).

FIG. 2E shows substrate-A 102 inverted and bonded to second substrate-B 104 employing bonding joint 106. Substrate-B 104 may be a second wafer, a second chip, a routing substrate, or the like.

After bonding to substrate-B 104, substrate-A 102 is thinned. The wafer may be thinned in a grinding, lapping, or polishing process. The wafer may be thinned to a range of several tens of microns, thus removing a portion of bulk layer 110.

Turning to FIG. 2F, the bulk layer 110 on the backside of substrate-A 102 is shown recessed to expose the bottom of liner 117. The recess process may be performed in a two-step process by, for example, a first CMP process and a second wet etch process. Alternatively, substrate 102 may be thinned and the backside of substrate-A 102 recessed in a single process step. The recess process may have a high etch selectivity between bulk layer 110 and liner 117.

Turning to FIG. 2G, passivation dielectric layer 250 is disposed. The passivation dielectric layer 250 serves as the hard mask for removing sacrificial material 226 from TSV structures 116 and serves as the passivation layer for the subsequent conductive material disposed in TSV structures 116. Passivation dielectric layer 250 may be a plasma enhanced USG material or other dielectric material.

The backside of substrate-A 102 is then planarized (again recall that the backside of substrate 102 is oriented up). A CMP process may be used for the planarization step. The CMP process may stop on liner 117, before exposing sacrificial material 226. A second wet or dry etch may be employed to expose sacrificial material 226. Alternatively sacrificial material 226 may be exposed in a one-step CMP or etch process. The etch of sacrificial material 226 may be implemented by a dry or wet method with the high selectivity between the sacrificial material 226 and the passivation dielectric layer 250.

The underlying bulk material is protected from the sacrificial material 226 etch by the passivation dielectric layer 250, which acts as a hard mask. Sacrificial material 226 etch stops at ESL 224. Next, ESL 224 is etched, exposing contact 230 for electrical interconnection.

As noted earlier the passivation dielectric layer 250 and the ESL material may be selected to have a high etch selectivity. Removal of ESL 224 allows access to contacts 230, which in turn electrically couples the TSV structures 116 to interconnect layer 108. The resulting structure is shown in FIG. 2H.

Turning to FIG. 2I, the TSV structures 116 are filled with conducting material 260. Metal, such as Al, Cu, alloys and the like may be sputtered, electro-plated, or screen-printed to fill TSV structures 116. Alternatively, other conductive materials may be used. Following the disposition of conducting material 260, substrate 102 may again be planarized by a CMP process.

The process is then completed by forming backside connection layer 112, as shown in FIG. 1. Backside connection layer 112 is comprised of a dielectric layer. For example, the dielectric layer may be formed by a SiN deposition, followed by a USG deposition. The dielectric layer may be patterned and etched. Backside metal 122 is formed by, for example, a damascene process or a patterning of a metal layer. Backside connection layer 112 may be comprised therefore of the SiN/USG dielectric layer and the backside metal 122. The substrate may then be bonded to further outside systems, using methods well known in the art. The resultant structure is shown in FIG. 1.

FIG. 3 is a flow chart of a method of forming a substrate within a semiconductor substrate stacking system. The process begins by etching TSV openings before the front end of line (FEOL) contact level (step 302) on a first substrate. The etched TSV is coated with a liner (step 304). The liner may act as a passivation layer providing a barrier between the substrate and the eventual conductive material in the finished TSV structure. The liner may be any dielectric, for example, a silicon nitride, a silicon oxide, or the like. An advantage of an illustrative embodiment is the quality of the dielectric that may be used for the liner at the pre-contact stage of processing. A high quality oxide may be used since no metals have been incorporated thus far in the process.

The TSV structure is then filled with a sacrificial material (step 306), forming a temporary plug in the TSV structure. The sacrificial material may be polysilicon, a dielectric, a polymer, any combination of these materials, or the like. A consideration in selecting a sacrificial material may be how the temporary material will be removed. A high selectivity between the sacrificial material and the subsequent hard mask may be desirable.

Following step 306, filling the TSV structure with sacrificial material, a dielectric etch stop layer (ESL) is disposed on top of the sacrificial material (step 308). The etch stop layer may be an oxide, nitride, other suitable dielectric, or the like. Following the ESL, the contact layer is formed (step 310). The contact layer comprises a dielectric layer or combination of dielectric layers, such as SiON, SiN, PSG and the like, and metal or conductive contacts, which may be W, Al, Cu, doped polysilicon, or the like.

Next, the interconnect layer is formed (step 312). The interconnect layer may be formed of Cu, Al, other metals, alloys, or conductive material combinations, sandwiched between inter-metal dielectric layers, which may be composed of FSG, USG, or the like. A top metal layer is formed which may be employed as a bonding joint (step 314).

The first substrate may then be inverted and bonded to a second substrate (step 316). In another embodiment, the second substrate may also have a TSV structure or structures and be stacked on a third substrate. In yet another embodiment, the first substrate may continue processing without bonding to another substrate.

The first substrate is then thinned (step 318). The thinning process may be done by mechanical cutting, wet or dry etching process.

The bulk material between the TSV structures is then recessed (step 320) to reveal the TSV structure liner (as shown in FIG. 2F). A hard mask is deposited (step 322) on the backside of the first substrate, covering the exposed TSV structure liner. The hard mask may be a dielectric and may be, for example, a plasma-enhanced USG. In addition to serving as a hard mask during the TSV structure sacrificial material removal, the hard mask serves as the passivation layer for the eventual TSV structure metal filling process.

The hard mask layer, disposed on the backside of the first substrate, is then planarized. The planarization may consist of, for example, a CMP process, which stops upon exposure of the liner (step 324). The planarized backside is then blanket etched to remove the exposed portion of the liner (step 326). Further, the blanket etch process may be a wet or dry etch. Alternatively, the CMP process may be extended to remove the exposed liner in one step (step 325). In either process, the sacrificial material in the TSV structure is exposed. A dry or wet etch may be used to remove the sacrificial material (328). The sacrificial material etch stops at the ESL layer. As noted above, a high selectivity between the hard mask and the ESL material may be desired.

The ESL is then etched (step 330), using either a wet or dry etch, as suitable. In an illustrative embodiment an anisotropic dry etch is implemented to limit the etch effect on liner 117.

The TSV structure is then filled with conductive material (step 332), for example, metals, metal alloys and the like. The filling process may be a sputter process, electro-plating process, a screen printing process, or the like. The metal surface of the backside of the first substrate is then planarized. A layer of SiN may be deposited followed by a dielectric layer of, for example, USG. The backside of the first substrate is then patterned and etched, to form openings or trenches to receive a further disposal of metal for the backside metal structures, thus forming backside connection layer (step 334). The substrate may be processed further with processes well known by those of ordinary skill in the art or the process may then end.

Although the illustrative embodiment and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the features and functions discussed above can be implemented in software, hardware, or firmware, or a combination thereof. As another example, it will be readily understood by those skilled in the art that layer compositions may be varied while remaining within the scope of the present invention.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

What is claimed is:
 1. An integrated circuit comprising: a substrate having an active region formed in a top surface of the substrate; a plurality of vias, each extending through the substrate, each having a first termination substantially aligned with a bottom surface of the substrate and a second termination substantially aligned to the top surface of the substrate; wherein each first termination of the plurality of vias terminate on a common plane at the bottom surface and are electrically insulated from one another; a first conductive contact electrically connected to the second termination of at least one of the vias and electrically connected to a conductive interconnect layer; a first bonding joint connected to the second termination of the via and extending above a topmost insulator of the substrate, wherein there is no semiconductor substrate between the top surface of the substrate and the first bonding joint; and a second conductive contact electrically connected to the conductive interconnect layer and the active region.
 2. The integrated circuit of claim 1 further comprising liner material substantially surrounding the respective vias and wherein the liner material does not surround the first conductive contact.
 3. The integrated circuit of claim 2, wherein the liner material comprises a dielectric material.
 4. The integrated circuit of claim 1, wherein the top surface of the substrate is a top surface of a semiconductor material.
 5. The integrated circuit of claim 1 further comprising a second substrate wherein the second substrate has a second bonding joint connected to the substrate.
 6. The integrated circuit of claim 5, wherein the first and second bonding joints are physically contacting.
 7. The integrated circuit of claim 5 further comprising: a contacting area_(cc) of the first conductive contact; and a contacting area_(via) of at least one of the vias, wherein contacting area_(cc) is less than contacting area_(via).
 8. The integrated circuit of claim 5, further comprising a plurality of first conductive contacts contacting a single via.
 9. The integrated circuit of claim 5, wherein a material of the first conductive contact is selected from the group consisting of Cu, W, alloy, or other conducting material.
 10. The integrated circuit of claim 1, wherein there is no bulk layer of semiconductive material between the top surface of the substrate and the first bonding joint.
 11. A semiconductor substrate structure, the structure comprising: a backside; a front-face; a bulk layer; an interconnect layer, wherein the interconnect layer includes a plurality of conductive layers sandwiched between inter-metal dielectric layers, the plurality of conductive layers being parallel to the front face; a contact layer, wherein the contact layer is between the bulk layer and the interconnect layer; a first through substrate via (TSV) commencing between the bulk layer and the contact layer and terminating at the backside of the bulk layer, wherein the first TSV is electrically coupled to the interconnect layer, and wherein the first TSV is electrically coupled to the backside; a bonding region on the front-face, wherein the interconnect layer is between the bonding region and the first TSV and wherein the bonding region extends beyond a topmost surface of a topmost insulator on the front face, wherein there is no semiconductor substrate between the front face and the bonding region; and a second TSV commencing between the bulk layer and the contact layer and terminating at the backside of the bulk layer, wherein the second TSV is electrically isolated from the first TSV.
 12. The structure of claim 11 further comprising: a lining, on sidewalls of the first TSV.
 13. The structure of claim 12, wherein the first TSV comprises a metal that is isolated from the bulk layer by the lining, and wherein the lining is limited to the bulk layer.
 14. The structure of claim 11 further comprising: a plurality of contacts, wherein the first TSV is electrically coupled to the interconnect layer at least through a first contact, and a circuit, wherein the circuit is electrically coupled to the interconnect layer at least through a second contact, wherein the first contact and the second contact are formed in the contact layer.
 15. The structure of claim 11 further comprising: a second substrate with a second bonding region, wherein the bonding region of the semiconductor substrate structure is bonded to the second bonding region of the second substrate.
 16. The structure of claim 11, wherein the bulk layer is silicon.
 17. The semiconductor substrate structure of claim 11, wherein there is no bulk layer of semiconductive material between the front face and the bonding region.
 18. A system of stacked semiconductor substrates, the system comprising: a first substrate including; a backside; a front-face; a bulk layer, wherein the bulk layer comprises a semiconductor material; a contact layer, wherein the contact layer is between the bulk layer and an interconnect layer; wherein the interconnect layer includes a plurality of inter-metal dielectric layers sandwiched between a plurality of conductive layers, the plurality of inter-metal dielectric layers and plurality of conductive layers being parallel to the front-face, and wherein the interconnect layer does not contain a semiconductor substrate; a plurality of lined TSVs commencing between the contact layer and terminating at the backside, wherein each lined TSV is electrically coupled to the interconnect layer and wherein each lined TSV is electrically coupled to a bonding pad on the backside, and further wherein each lined TSV is electrically isolated from an adjacent TSV; and a bonding joint, wherein the bonding joint is on the front-face and is electrically and physically connected to the interconnect layer and further wherein the bonding joint extends beyond a top surface of a topmost insulator layer on the front face; and a second substrate bonded to the first substrate at the bonding joint.
 19. The system of stacked semiconductor substrates of claim 18, wherein a lining is disposed into each lined TSV prior to any first substrate metal processes.
 20. The system of stacked semiconductor substrates of claim 18, wherein a bonding metal at the bonding joint is selected from the group consisting of Cu, W, Au, Sn, Pb and an alloy thereof.
 21. The system of stacked semiconductor substrates of claim 18, wherein the interconnect layer does not contain a bulk layer of semiconductive material.
 22. A semiconductor device comprising: a first substrate comprising: a bulk semiconductor layer having a top surface and a bottom surface; an active region formed in the top surface of the bulk semiconductor layer; a first TSV extending through the bulk semiconductor layer; a second TSV extending through the bulk semiconductor layer, wherein the first and second TSVs each have a first termination at the top surface of the bulk semiconductor layer and a second termination at the bottom surface of the bulk semiconductor layer, and wherein the first TSV is electrically isolated from the second TSV; a first conductive contact electrically and physically connected to the first termination of the first TSV; and a second conductive contact electrically and physically connected to the active region; an interconnect layer comprising a plurality of inter-metal dielectric layers sandwiched between a plurality of conductive layers, wherein the first and second conductive contacts are electrically and physically connected to the interconnect layer, and wherein the interconnect layer does not contain a semiconductor substrate; and a first bonding joint electrically and physically connected to the interconnect layer and electrically connected to the first TSV, the first bonding joint extending beyond a top surface of a topmost insulator layer of the interconnect layer.
 23. The semiconductor device of claim 22 further comprising a second substrate wherein the second substrate has a second bonding joint, the second bonding joint electrically and physically connected to the first bonding joint.
 24. The semiconductor device of claim 23, wherein the first bonding joint comprises a material selected from a group consisting essentially of W, Al, Cu, Sn, Pb, or a combination thereof.
 25. The semiconductor device of claim 22, wherein the interconnect layer does not contain a bulk semiconductive layer.
 26. The semiconductor device of claim 22 further comprising a liner material on the sidewalls of the first TSV and the second TSV.
 27. The semiconductor device of claim 22, wherein the first conductive contact comprises a plurality of conductive contacts contacting the first TSV.
 28. The semiconductor device of claim 22, wherein the first conductive contact has a first contacting area, and wherein the first TSV has a second contacting are, the first contacting area being less than the second contacting area.
 29. The semiconductor device of claim 22, wherein the first and second conductive contacts comprise a material selected from a group consisting essentially of W, Al, Cu, doped polysilicon, or a combination thereof.
 30. The semiconductor device of claim 22, wherein the conductive layers in interconnect layer comprise a material selected from a group consisting essentially of W, Al, Cu, or a combination thereof. 